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1 for more information www.linear.com/LTC7860 typical a pplica t ion fea t ures descrip t ion high efficiency switching surge stopper the lt c ? 7860 high efficiency surge stopper protects loads from high voltage transients . high efficiency permits higher currents and smaller solution sizes . during an input overvoltage event, such as a load dump in vehicles, the LTC7860 controls the gate of an external mosfet to act as a switching dc/dc regulator ( protective pwm mode). this operation regulates the output voltage to a safe level, allowing the loads to operate through the input over-voltage event . during normal operation (switch- on mode), the LTC7860 turns on the external mosfet continuously, passing the input voltage through to the output. an internal comparator limits the voltage across the current sense resistor and regulates the maximum output current to protect against overcurrent faults. an adjustable timer limits the time that the LTC7860 can spend in overvoltage or overcurrent regulation. when the timer expires, the external mosfet is turned off until the LTC7860 restarts after a cool down period . by strictly limiting the time in protective pwm mode when the power loss is high, the components and thermal design can be optimized for normal operation and safely oper - ate through high voltage input surges and/or overcurrent faults. an additional pmos can be added for reverse battery protection. a pplica t ions n high effciency v out clamp stops high voltage input surges n switch-on mode 100% duty cycle for normal operation n protective pwm mode for transients and faults n v in pin to sgnd range: 3.5v to 60v n external input voltage is extendable to 200v + n adjustable output voltage clamp n adjustable output overcurrent protection n power inductor improves input emi in normal operation n programmable fault timer n adjustable soft-start for input inrush current limiting n 4.5% retry duty cycle during faults n adjustable switching frequency: 50khz to 850khz n optional reverse input voltage protection n available in thermally enhanced 12-lead msop package n industrial and automotive power n telecom power n vehicle power including iso7637 n military power including mil1275 l , lt , lt c , lt m , opti - loop, linear technology, burst mode and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s . patents including 5731694. 7860 ta01a 10k 0.1f 0.1f 22f tmr sgnd ss v fb ith v fbn run cap freq sense vin gate pgnd LTC7860 v in 60v max 12v nom 3.5v min v out 18v max 12v nom 3.5v min 5a 18v adjustable clamp c tmr = 22f 60v input surge to 18v during a v in surge protective pwm: v out clamped 100ms/div v in 10v/div v out 10v/div v tmr 1v/div LTC7860 7860 ta01b 7860f 6.8h 12m 1m 48.7k 10f 10f 0.47f 680pf
2 for more information www.linear.com/LTC7860 a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... C0. 3 v to 65 v v in -v sense voltage ...................................... C0. 3 v to 6v v in -v cap voltage ........................................ C 0.3 v to 10 v run voltage ............................................... C0.3 v to 65 v v fbn , tmr voltages ..................................... C 0.3 v to 6v ss , ith , freq , v fb voltages ........................ C 0.3 v to 5v operating junction temperature range ( n otes 3 , 4) ........................................ C 55 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ms op package ................................................. 300 c o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC7860emse#pbf LTC7860emse#trpbf 7860 12-lead plastic msop C40c to 125c LTC7860imse#pbf LTC7860imse#trpbf 7860 12-lead plastic msop C40c to 125c LTC7860hmse#pbf LTC7860hmse#trpbf 7860 12-lead plastic msop C40c to 150c LTC7860mpmse#pbf LTC7860mpmse#trpbf 7860 12-lead plastic msop C55c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion (notes 1, 2) 1 2 3 4 5 6 tmr freq sgnd ss v fb ith 12 11 10 9 8 7 gate v in sense cap run v fbn top view 13 pgnd mse package 12-lead plastic msop t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad (pin 13) is pgnd, must be soldered to pcb LTC7860 7860f
3 for more information www.linear.com/LTC7860 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units input supply v in input voltage operating range 3.5 60 v v uvlo undervoltage lockout (v in -v cap ) ramping up threshold (v in -v cap ) ramping down threshold hysteresis l l 3.25 3.00 3.50 3.25 0.25 3.8 3.50 v v v i q input dc supply current freq = 0v, v fb = 0.83v (no load) 0.77 1.2 ma shutdown supply current run = 0v 7 12 a output sensing v reg regulated feedback voltage v reg = (v fb C v fbn ) v ith = 1.2v (note 4) l 0.791 0.800 0.809 v feedback voltage line regulation v in = 3.8v to 60v (note 4) C0.005 0.005 %/v feedback voltage load regulation v ith = 0.6v to 1.8v (note 4) C0.1 C0.015 0.1 % g m(ea) error amplifier transconductance v ith = 1.2v, ?i ith = 5a (note 4) 1.8 ms i fb feedback input bias current C50 C10 50 na i fbn feedback negative input bias current C50 C10 50 na current sensing v ilim current limit threshold (v in -v sense ) v fb = 0.77v l 85 95 103 mv i sense sense pin input current v sense = v in 0.1 2 a start-up and shutdown v run run pin enable threshold v run rising l 1.22 1.26 1.32 v run pin hysteresis 150 mv i ss soft-start pin charging current v ss = 0v 10 a fault timer i tpu tmr pull-up current tmr = 1.1v, v fb = 0.83v l C35 C30 C25 a i tpdr tmr pull-down current restart tmr = 1.1v, v fb = 0.77v 40 a i tpdc tmr pull-down current cool down tmr = 1.1v, v fb = 0.77v 1.0 1.3 1.6 a v gth tmr gate off threshold v fb = 0.77v l 1.25 1.29 1.35 v v rth tmr restart threshold v fb = 0.77v 240 mv t seti(1f) tmr set time initial for fault detection for 1f (t seti = v gth /i tpu ) l 37 44 50 ms/f t setr(1f) tmr set time repeat for fault detection for 1f (t seti = (v gth C v rth )/i tpu ) 32 ms/f t rstc(1f) tmr restart cool down time for 1f (t rstc = (v gth C v rth )/i tpdc ) 732 ms/f dty tstr tmr restart duty cycle in a sustained fault ( dty tstr = t setr /t rstc ) l 3.5 4.5 5.5 % switching frequency the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 3) v in = 12v, unless otherwise noted. LTC7860 7860f
4 for more information www.linear.com/LTC7860 symbol parameter conditions min typ max units programmable switching frequency r freq = 24.9k r freq = 64.9k r freq = 105k 375 105 440 810 505 khz khz khz low switching frequency freq = 0v 320 350 380 khz high switching frequency freq = open 485 535 585 khz f fold foldback frequency as percentage of programmable frequency v fb = 0v, freq = 0v 18 % t on(min) minimum on-time 220 ns gate driver v cap gate bias ldo output voltage (v in -v cap ) i gate = 0ma l 7.6 8.0 8.5 v r up gate pull-up resistance gate high 2 r dn gate pull-down resistance gate low 0.9 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 3) v in = 12v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) as follows: t j = t a + (p d ? ja ) where ja (in c/w) is the package thermal impedance provided in the pin configuration section for the corresponding package. note 3: the LTC7860 is tested under pulsed load conditions such that t j t a . the LTC7860e is guaranteed to meet performance specifications from 0c to 85c operating junction temperature range. the LTC7860e specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC7860i is guaranteed to meet performance specifications over the C40c to 125c operating junction temperature range, the LTC7860h is guaranteed over the C40c to 150c operating junction temperature range, and the LTC7860mp is guaranteed and tested over the full C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 4: the LTC7860 is tested in a feedback loop that adjust v reg or (v fb C v fbn ) to achieve a specified error amplifier output voltage (on ith pin). LTC7860 7860f
5 for more information www.linear.com/LTC7860 typical p er f or m ance c harac t eris t ics gate bias ldo (v in - v cap ) load regulation gate bias ldo (v in - v cap ) dropout behavior current sense voltage over ith voltage current sense voltage over temperature ss pin pull-up current over temperature frequency over input voltage frequency over temperature frequency foldback % over feedback voltage t a = 25c, unless otherwise noted. v in (v) 0 300 f (khz) 450 600 550 500 400 350 10 20 30 40 50 7860 g19 60 freq = 0v freq = open v fb (mv) 0 0 frequency foldback (%) 60 120 100 80 40 20 200 400 600 7860 g21 800 i gate (ma) 0 ?3.5 (v in - v cap ) regulation (%) ?2.0 0.5 ?1.0 ?0.5 0.0 ?1.5 ?2.5 ?3.0 5 10 15 7860 g22 20 i gate (ma) 0 ?0.5 (v in - v cap ) dropout (v) 0.1 v in = 5v ?0.1 0.0 ?0.2 ?0.3 ?0.4 5 10 15 7860 g23 20 temperature (c) ?75 90 current limit sense voltage (mv) 100 98 94 92 96 ?25 25 75 125 7860 g25 175 temperature (c) ?75 300 f (khz) 450 600 550 500 400 350 ?25 25 75 125 7860 g20 175 freq = 0v freq = open temperature (c) ?75 6 ss pull-up current (a) 14 12 8 10 ?25 25 75 125 7860 g26 175 v ss = 0v ith voltage (v) 0 ?10 current sense voltage (mv) 100 80 90 40 30 20 10 0 70 60 50 0.4 0.8 1.2 1.6 7860 g24 2 100 125 150 175 ?35.0 ?32.5 ?30.0 ?27.5 ?25.0 tmr pull?up current (a) temperature tmr pull-up current over 7860 g27 LTC7860 7860f temperature (c) ?75 ?50 ?25 0 25 50 75
6 for more information www.linear.com/LTC7860 p in func t ions tmr ( pin 1): programmable fault timer. the tmr function monitors the time spent in protective pwm mode and provides fault control. during a fault, a 30a (i tpu ) current pulls up the tmr pin. if the fault clears before the 1.29v tmr gate off threshold (v gth ) is reached, a 40 a current (i tpdr ) resets the tmr pin to ground. the gate turns off and shuts down when v gth is reached. in shutdown, a 1.3a (i tpdc ) current pulls tmr down to a 240 mv tmr restart threshold (v rth ) allowing a cool down period before restart. freq (pin 2): switching frequency setpoint input. the switching frequency is programmed by an external set- point resistor r freq connected between the freq pin and signal ground. an internal 20 a current source creates a voltage across the external setpoint resistor to set the internal oscillator frequency. alternatively, this pin can be driven directly by a dc voltage to set the oscillator frequency. grounding selects a fixed operating frequency of 350 khz. floating selects a fixed operating frequency of 535khz. sgnd (pin 3): ground reference for small-signal analog component ( signal ground). signal ground should be used as the common ground for all small-signal analog inputs and compensation components. connect the signal ground to the power ground ( ground reference for power components) only at one point using a single pcb trace. ss (pin 4): soft-start and external tracking input. the LTC7860 regulates the feedback voltage to the smaller of 0.8v or the voltage on the ss pin. an internal 10 a pull-up current sour ce is connected to this pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. v fb (pin 5): output feedback sense. a resistor divider from the regulated output point to this pin sets the output voltage. the LTC7860 will nominally regulate v fb to the internal reference value of 0.8 v. if v fb is less than 0.4v, the switching frequency will linearly decrease and fold back to about one-fifth of the internal oscillator frequency to reduce the minimum duty cycle. ith (pin 6): current control threshold and controller compensation point. this pin is the output of the error amplifier and the switching regulators compensation point. the voltage ranges from 0 v to 2.9 v, with 0.8 v cor - responding to zero sense voltage (zero current). v fbn ( pin 7): feedback input for an inverting feedback option. connect v fbn to the center of a resistor divider between the output and v fb . the v fbn threshold is 0v. to defeat the inverting amplifier and use non-inverting feedback option, tie v fbn > 2 v. v fbn can be tied to freq if freq is floated and a 535 khz fixed operating frequency is selected . the minimum suggested value of the feedback resistor between v fb and v fbn for inverting feedback option is 10k. run (pin 8): run control input. a run voltage above the 1.26 v threshold enables normal operation, while a voltage below the threshold shuts down the controller. an internal 0.4 a current source pulls the run pin up to about 3.3 v. the run pin can be connected to an external power supply up to 60v. cap (pin 9): gate driver (C) supply. a low esr ceramic bypass capacitor of at least 0.47 f or 10 x the effective c miller of the p-channel power mosfet, is required from v in to this pin to serve as a bypass capacitor for the internal regulator. to ensure stable low noise operation, the bypass capacitor should be placed adjacent to the v in and cap pins and connected using the same pcb metal layer. sense (pin 10): current sense input. a sense resistor, r sense , from the v in pin to the sense pin sets the maxi- mum current limit. the peak inductor current limit is equal to 95mv/r sense . for accuracy, it is important that the v in pin and the sense pin route directly to the current sense resistor and make a kelvin (4-wire) connection. v in (pin 11): chip power supply. a minimum bypass capacitor of 0.1 f is required from the v in pin to power ground. for best performance use a low esr ceramic capacitor placed near the v in pin. LTC7860 7860f
7 for more information www.linear.com/LTC7860 p in func t ions f unc t ional diagra m gate (pin 12): gate drive output for external p-channel mosfet. the gate driver bias supply voltage (v in -v cap ) is regulated to 8 v when v in is greater than 8 v. the gate driver is disabled when (v in -v cap ) is less than 3.5v ( typi- cal), 3.8 v maximum in start-up and 3.25v (typical) 3.5v maximum in normal operation. pgnd ( exposed pad pin 13): ground reference for power components ( power ground). the pgnd exposed pad must be soldered to the circuit board for electrical contact and for rated thermal performance of the package. connect signal ground to power ground only at one point using a single pcb trace. ? + ea (g m = 1.8ms) 0.8v en 10a logic control ldo in out pll system q s r r vco gate off slope compensation 3.25v gate cap ss v fbn v in ? 8v sense v in 1.26v ? + + pgnd c cap mp 0.5a uvlo r freq sgnd freq run run 0.4a 20a 7860 fd tmr + ? ? + ? drv + ? ith r ith c ith1 c tmr cool down c ss z 1 c in vin r sense c out v out v fb r fb1 r z1 r fb2 icmp + v in normal operation + ? v rth 0.24v v gth 1.29v + ? i tpdc 1.3a i tpdr 40a i tpu 30a fault timer logic high current path LTC7860 7860f
8 for more information www.linear.com/LTC7860 o pera t ion high efficiency switching surge stopper overview the LTC7860 is designed for use as a high efficiency switching surge stopper and/or input inrush current lim - iter. normal operation for the LTC7860 is in " dropout" or switch- on mode. the LTC7860 switches during start- up or in response to either an input over-voltage or output short-circuit event (protective pwm mode). if the time spent switching exceeds the time programmed by the timer the LTC7860 will shut down. a high efficiency surge stopper or input inrush current limiter can be thought of as a pre-regulator. as an example of a mil1275 application, the input voltage connects to a 28 v vehicle power bus. the 28 v power bus can go as high as 100 v with a surge profile lasting up to 500 ms. the output must be pre-regulated or limited to 34 v maximum and can go as low as 12 v during engine cranking. the LTC7860 limits the voltage seen at the output and pro - tects any load connected to the 28 v bus from potentially destructive voltage levels. the LTC7860 timer limits the time spent switching where excessive and thermally destructive power loss can occur. for both a linear surge stopper such as the ltc4363 and the LTC7860 switching surge stopper, the power loss increases significantly once regulation begins. in a linear surge stopper, the power loss is the power loss of the regulating mosfet. in a high efficiency surge stopper or switching surge stopper, internal power loss is determined by conversion efficiency. a switching surge stopper will allow higher output current and power levels than a com - parable linear solution by virtue of reduced power loss. in a switching surge stopper the internal surge power loss can increase by as much as 10 times the normal power loss. if the time spent in pwm mode regulation is limited, the operating power can be pushed beyond what can be achieved in steady state operation. this is precisely the same concept as utilized in linear surge stoppers but extended to a switching supply. the use of the timer improves reliability and reduces component size when compared to a continuous solution. by limiting the time in regulation when the power loss is high, the components and thermal design can be optimized for normal operation and safely operate through high voltage input surges and/ or overcurrent faults. in a switching surge stopper the insertion loss in normal operation or switch-on mode is the primary consider- ation and not efficiency in switching. the LTC7860 circuit must operate without damage during a surge or fault event. the switching surge stopper is effectively a wire in normal operation where the insertion loss is determined by multiplying the input current by the effective resistance. LTC7860 main control loop the LTC7860 uses a peak current- mode control architecture to regulate the output in a step-down dc/ dc switching regulator. the v fb input is compared to an internal reference by a transconductance error amplifier (ea). the internal reference can be either a fixed 0.8v reference v ref or the voltage input on the ss pin. in normal operation v fb regulates to the internal 0.8v reference voltage. in soft-start, when the ss pin voltage is less than the internal 0.8 v reference voltage, v fb will regulate to the ss pin voltage. the error amplifier output connects to the ith (current [ i] threshold [ th]) pin. the voltage level on the ith pin is then summed with a slope compensation ramp to create the peak inductor current set point. the peak inductor current is measured through a sense resistor, r sense , placed across the v in and sense pins. the resultant differential voltage from v in to sense is proportional to the inductor current and is compared to the peak inductor current setpoint. during normal opera - tion the p-channel power mosfet is turned on when the clock leading edge sets the sr latch through the s input. the p-channel mosfet is turned off through the sr latch r input when the differential voltage from v in to sense is greater than the peak inductor current setpoint and the current comparator, icmp, trips high. LTC7860 7860f
9 for more information www.linear.com/LTC7860 o pera t ion power cap and v in undervoltage lockout (uvlo) power for the p-channel mosfet gate driver is derived from the cap pin. the cap pin is regulated to 8 v below v in in order to provide efficient p-channel operation. the power for the v cap supply comes from an internal ldo, which regulates the v in -cap differential voltage. a mini- mum capacitance of 0.47f ( low esr ceramic) is required between v in and cap to assure stability. for v in 8 v, the ldo will be in dropout and the cap volt- age will be at ground, i.e., the v in -cap differential voltage will equal v in . if v in -cap is less than 3.25v ( typical), the LTC7860 enters a uvlo state where the gate is prevented from switching and most internal circuitry is shut down. in order to exit uvlo, the v in -cap voltage would have to exceed 3.5v (typical). shutdown and soft-start when the run pin is below 0.7 v, the controller and most internal circuits are disabled. in this micropower shutdown state, the LTC7860 draws only 7 a. releasing the run pin allows a small internal pull-up current to pull the run pin above 1.26 v and enable the controller. the run pin can be pulled up to an external supply of up to 60 v or driven directly by logic levels. the start-up of the output voltage v out is controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the 0.8 v internal reference, the v fb pin is regulated to the voltage on the ss pin. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to signal ground. an internal 10 a pull-up current charges this capacitor, creating a voltage ramp on the ss pin. as the ss volt - age rises from 0 v to 0.8 v, the output voltage v out rises smoothly from zero to its final value. the ss time must be sufficiently less than the tmr set time to avert a timer shutdown in startup or fault recovery. if the slew rate of the ss pin is greater than 1.2 v/ms, the output will track an internal soft-start ramp instead of the ss pin. the internal soft-start will guarantee a smooth start-up of the output under all conditions, including in the case of a short-circuit recovery where the output voltage will recover from near ground. frequency selection the switching frequency of the LTC7860 can be selected using the freq pin. the freq pin can be tied to signal ground, floated, or programmed through an external re - sistor. t ying freq pin to signal ground selects 350khz, while floating selects 535 khz. placing a resistor between freq pin and signal ground allows the frequency to be programmed between 50 khz and 850 khz. refer to the chart in the application section for switching frequency versus resistor values. fault protection in the event of an output short-circuit or overcurrent con - dition that causes the output voltage to drop significantly while in current limit, the LTC7860 operating frequency will fold back. anytime the output feedback v fb voltage is less than 50% of the 0.8 v internal reference (i.e., 0.4v), frequency foldback is active. the frequency will continue to drop as v fb drops until reaching a minimum foldback frequency of about 18% of the setpoint frequency. fre- quency foldback is designed, in combination with peak current limit, to limit current in start-up and short-circuit conditions. setting the foldback frequency as a percentage of operating frequency assures that start - up characteristics scale appropriately with operating frequency. LTC7860 7860f
10 for more information www.linear.com/LTC7860 the LTC7860 is a high efficiency switching surge stopper which provides input voltage surge protection, input inrush current limiting and output short protection. high efficiency switching permits high output current capability and small solution size. during an input overvoltage event, such as a load dump in vehicles, the LTC7860 controls the gate of an external mosfet to act as a switching dc/dc regulator (protective pwm mode). this operation regulates the output voltage to a safe level, allowing the loads to operate through the input over-voltage event. during normal operation ( switch- on mode), the LTC7860 turns on the external mosfet continuously, passing the input voltage through to the output. an internal comparator limits the voltage across the current sense resistor and regulates the maximum output current to protect against over current faults. o utput v ol tage p rogramming the LTC7860 is highly flexible and offers application options to address a variety of input and output voltage ranges. these options are best divided into two categories. the first category is operation at or below v in ?=?60 v. the second category is operation above 60 v. the LTC7860 input and output voltage operation in the second category depends only on external components and can be reliably extended up to 200v. operation for v in of 60v and below for operation at v in of 60 v and below, the output voltage is programmed by connecting a feedback resistor divider from the output to the v fb pin as shown in figure 1 a. the front page application is an example of this configuration. the output voltage in steady state operation is set by the feedback resistors r fb 2 and r fb 1 according to the equation : v out = 0.8v ? 1 + r fb1 r fb2 ? ? ? ? ? ? great care should be taken to route the v fb line away from noise sources, such as the inductor or the gate signal that drives the external p mosfet. the best practice is to locate resistors r fb2 and r fb1 and capacitor c ff local a pplica t ions i n f or m a t ion to the LTC7860 to keep the v fb trace short and without vias. the planes for v out and gnd are then routed to the desired regulation point. detailed layout suggestions are discussed in the layout sections later in the data sheet. the feed-forward capacitor c ff is added to improve transient response. operation for v in above 60v for operation at v in = 60 v, a floating ground must be cre- ated by a bootstrapped shunt regulator such as a zener or similar element. to establish shunt dc bias to the LTC7860, connect the floating ground to the LTC7860 pgnd and sgnd pins. the zener voltage or shunt dc bias limit is typically 12 v to minimize internal power dissipation but can be extended up to 60 v. the v in operational input voltage ranges for these applications are limited only by external components and can reliably extend to 200 v and beyond. there are two feedback options for operation above 60v which are inverting and non-inverting feedback. the inverting feedback option uses fewer components with slightly reduced accuracy (figure 1 b). the non- inverting feedback option uses additional components but with bet - ter accuracy ( figure 1 c). it has the additional advantage of reducing vin quiescent current in normal operation. inverting feedback option in the inverting feedback option for v in above 60 v, the voltage is programmed by connecting a feedback resistor divider from the output to ground as shown in figure ?1 b. v out is divided down and the voltage presented to the gate of q fb . the gate voltage is then translated into a signal current by q fb and r fb3 and sent to the LTC7860 floating ground inverting feedback pin v fbn . the resistor r fb4 LTC7860 v fb v fbn v out r fb2 r z1 c ff r fb1 7860 f01a z1 pgnd sgnd figure 1a. switching surge stopper for v in operation of 60v and below (v fbn > 2v) LTC7860 7860f
11 for more information www.linear.com/LTC7860 LTC7860 v in v in v out v fb v fbn r fb4 c fb4 r fb3 7860 f01b r fb2 c ff r fb1 z1 pgnd sgnd floating gnd q fb figure 1b. switching surge stopper for v in operation above 60v with inverting feedback a pplica t ions i n f or m a t ion translates the signal current proportional to v out into a feedback voltage between v fb and v fbn . the voltage at v fbn is the input of an inverting amplifier and is nominally equal to the floating ground. the output voltage in steady state operation is set by the feedback resistors according to the equation: v out = 0.8v ? r fb3 r fb4 + vgs qfb ? ? ? ? ? ? ? 1 + r fb2 r fb1 ? ? ? ? ? ? the shunt dc bias or zener and floating ground permits the drain current of q fb to be translated to a differential feedback voltage v fb C v fbn independent of the value of v in . r fb4 should be greater than 10 k to avoid v fb pin output current limitations. the integrator capacitor, c fb4 , should be sized to ensure the negative sense amplifier gain rolls off and limits high frequency gain peaking in the dc/dc control loop. the integrator capacitor pole can be safely set to be two times the switching frequency without affecting the dc/ dc phase margin according to the following equation. it is highly recommended that c fb4 be used in most applications. c fb4 = 1 2 t 2 t r fb4 t freqsw ( ) great care should be taken to route the v fb and v fb lines away from noise sources, such as the inductor or the gate signal that drives the external p mosfet. non-inverting feedback option in the non-inverting feedback option for v in above 60v, the voltage is programmed by connecting a feedback resistor divider from the output to ground as shown in figure?1 c. v out is divided down and the voltage presented to the base of q fb . the base voltage is then translated into a signal current by q fb and r fb3 and sent to pnp mirror q fbm1 , r fbm1 , q fbm2 and r fbm2 . in the non-inverting option, the internal inverting ampli- fier must be defeated by tying v fbn greater than 2 v. in figure 1 c, r z2 and z2 are used to tie v fbn high where z2 is chosen greater than 2 v but less than 6 v. v fbn may also be tied to the freq pin when the pin is floated and a fixed 535khz switching frequency is selected. choosing a fixed 535khz in the non-inverting option can simplify the pcb design and reduce component count. for the non- inverting option, an npn is used for q fb, which results in greater accuracy. the resistor r fb4 translates the signal current proportional to v out into a feedback voltage applied directly to the v fb pin. the v fbn pin is tied high and the inverting amplifier is defeated. the output voltage in steady state operation is set by the feedback resistors according to the equation: v out = 0.8v ? r fb3 r fb4 + vbe qfb ? ? ? ? ? ? ? 1 + r fb2 r fb1 ? ? ? ? ? ? LTC7860 v in v in v out v fb v fbn r fbm2 r fb4 7860 f01c r fb2 c ff r fb1 z1 pgnd sgnd floating gnd r fb3 r fbm1 q fbm2 q fb q fbm1 z2 r z2 figure 1 c. switching surge stopper with v in operation above 60v with non-inverting feedback LTC7860 7860f
12 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion s witching f requency the choice of operating frequency is a trade-off between efficiency and component size. lowering the operating fre - quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size.the switching frequency and resulting switching power loss are of secondary concern. it is generally recommended to go with as high a switching frequency as practical so as to limit the overall solution size. the free - running switching frequency can be programmed from 50 khz to 850 khz by connecting a resistor from freq pin to signal ground. the resulting switching frequency as a function of resistance on the freq pin is shown in figure 2. figure 2. switching frequency vs resistor on freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3863 f02 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 i nductor s election a reasonable starting point for ripple current is 70% of i out( max) at maximum v in . the largest ripple current occurs at the highest v in . to guarantee that the ripple current does not exceed a specified maximum, the inductance should be chosen according to: l = v out f ? ? i l(max) ? ? ? ? ? ? 1? v out v in(max) ? ? ? ? ? ? select an inductor with a saturation current rating sufficient to cover peak current during a full load input transient or output over load. powder core inductors are typically a good choice as they tend to be small and have good saturation characteristics. c urrent s ensing and c urrent l imit p rogramming the LTC7860 senses the inductor current through a cur - rent sense resistor, r sense , placed across the v in and sense pins. the voltage across the resistor, v sense , is proportional to inductor current and in normal operation is compared to the peak inductor current setpoint. an inductor current limit condition is detected when v sense exceeds 95mv. when the current limit threshold is exceeded, the p-channel mosfet is immediately turned off by pulling the gate voltage to v in regardless of the controller input. the peak inductor current limit is equal to: i l(peak) ? 95mv r sense ? ? ? ? ? ? this inductor current limit would translate to an output current limit based on the inductor ripple and duty factor: i out(limit) = 95mv r sense ? ? i l 2 ? ? ? ? ? ? the sense pin is a high impedance input with a maximum leakage of 2 a. since the LTC7860 is a peak current mode controller, noise on the sense pin can create pulse width jitter. careful attention must be paid to the layout of r sense . to ensure the integrity of the current sense signal, v sense , the traces from v in and sense pins should be short and run together as a differential pair and kelvin (4-wire) connected across r sense (figure 3). LTC7860 7860f
13 for more information www.linear.com/LTC7860 figure 3. inductor current sensing v in r sense LTC7860 v in sense r f mp optional filtering 7860 f03 c f a pplica t ions i n f or m a t ion the LTC7860 has internal filtering of the current sense voltage which should be adequate in most applications. however, adding a provision for an external filter offers added flexibility and noise immunity, should it be neces - sary. the filter can be created by placing a resistor from the r sense resistor to the sense pin and a capacitor across the v in and sense pins. it is important that the v in plane be a clean low inductance connection with minimal pcb via's. the maximum output current in switch-on mode is greater than the maximum current in protective pwm mode by one half the ripple current. the switch- on mode power path components must be designed to support the maximum power seen at the non-switching current limit setting. p ower mosfet s election the LTC7860 drives a p-channel power mosfet that serves as the main switch for the nonsynchronous inverting converter . important p-channel power mosfet parameters include drain-to-source breakdown voltage, on-resistance r ds(on) , threshold voltage v gs(th) , and the mosfet s thermal resistance jc( mosfet) and ja( mosfet) . the drain-to-source breakdown voltage must meet the following condition: bv dss > v in(max) the most important parameter for selection of the pmos switch ( after voltage rating) is r ds(on) . this will determine pmos loss during switch-on operation. the gate driver bias voltage v in -v cap is set by an internal ldo regulator. in normal operation, the cap pin will be regulated to 8 v below v in . a minimum 0.47 f capacitor is required across the v in and cap pins to ensure ldo stability. if required, additional capacitance can be added to accommodate higher gate currents without voltage droop. in shutdown and burst mode operation, the cap ldo is turned off. in the event of cap leakage to ground, the cap voltage is limited to 9 v by a weak internal clamp from v in to cap. as a result, a minimum 10 v v gs rated mosfet is required. d iode s election when the p-channel mosfet is turned off, a commutating diode carries the inductor current. this diode is only used during switching and does not conduct in switch-on mode. the average forward diode current is described as: i f( avg ) = i out ? (1 C d) the worst-case condition for diode conduction is a short circuit condition where the diode must handle the maximum current as the p- channel mosfet s duty factor approaches 0%. the diode therefore must be chosen carefully to meet worstcase voltage and current requirements. a good practice is to choose a diode that has a forward current rating higher than i out(max) . the diode reverse breakdown voltage must meet the fol- lowing condition: v r > v in(max) c in and c out s election (b uck m ode ) the input capacitance, c in , is required to filter the square wave current through the p-channel mosfet. use a low esr capacitor sized to handle the maximum rms current: i cin(rms) = i out(max) s v out v in s v in v out ? 1 LTC7860 7860f
14 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion the formula has a maximum at v in = 2v out , where i cin(rms) ?=? i out(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple cur - rent ratings from capacitor manufacturers are often based on only 2000 hours of life. ripple currents will only be applied during protective pwm operation, so de-rating requirements are minimal. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the ?v out is approximately bounded by: ? v out ? i l esr + 1 8 ? f ? c out ? ? ? ? ? ? since ?i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, specialty polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. specialty polymer capacitors offer very low esr but have lower specific capacitance than other types. tantalum capacitors have the highest specific capacitance , but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. e xternal s of t -s t art start-up characteristics are controlled by the voltage on the ss pin. when the voltage on the ss pin is less than the internal 0.8 v reference, the LTC7860 regulates the v fb pin voltage to the voltage on the ss pin. when the ss pin is greater than the internal 0.8 v reference, the v fb pin voltage regulates to the 0.8 v internal reference. the ss pin is used to program an external soft-start function. the primary function of the external soft start feature for a switching surge stopper is as an inrush current limiter in startup and fault recovery. soft- start is enabled by connecting a capacitor from the ss pin to ground. an internal 10 a current source charges the capacitor, providing a linear ramping voltage at the ss pin that causes v out to rise smoothly from 0 v to its final value. the total soft- start time will be approximately: t ss = c ss ? 0.8v 10a s hort - c ircuit f aults : c urrent l imit and f oldback the inductor current limit is inherently set in a current mode controller by the maximum sense voltage and r sense . in the LTC7860, the maximum sense voltage is 95 mv, mea- sured across the inductor sense resistor, r sense , placed across the v in and sense pins. the output current limit is approximately: i limit(min) = 95mv r sense ? ? i l 2 ? ? ? ? ? ? the current limit must be chosen to ensure that i limit(min) ? >? i out(max) under all operating conditions. short- circuit fault protection is assured by the combination of current limit and frequency foldback. when the output feedback voltage, v fb , drops below 0.4 v, the operating frequency, f, will fold back to a minimum value of ?t f when v fb reaches 0 v. both current limit and frequency foldback are active in all modes of operation. in a short- circuit fault condition, the output current is first limited by current limit and then further reduced by folding back the operating frequency as the short becomes more se - vere. the worst-case fault condition occurs when v out is shorted to ground. s hor t - c ircuit r ecover y and i nternal s of t - s t art an internal soft-start feature guarantees a maximum posi - tive output voltage slew rate in all operational cases. in a short-cir cuit recovery condition for example, the output recovery rate is limited by the internal soft-start so that LTC7860 7860f
15 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion output voltage overshoot and excessive inductor current buildup is prevented. the internal soft-start voltage and the external ss pin operate independently. the output will track the lower of the two voltages. the slew rate of the internal soft-start voltage is roughly 1.2 v/ms, which translates to a total soft-start time of 650 s. if the slew rate of the ss pin is greater than 1.2 v/ms the output will track the internal soft- start ramp. to assure robust fault recovery, the internal soft-start feature is active in all operational cases. if a short-circuit condition occurs which causes the output to drop significantly, the internal soft-start will assure a soft recovery when the fault condition is removed. the internal soft-start assures a clean soft ramp-up from any fault condition that causes the output to droop, guar - anteeing a maximum ramp rate in soft-start, short-circuit fault release. figure 4 illustrates how internal soft-start controls the output ramp-up rate under varying scenarios. v in u ndervoltage l ockout (uvlo) the LTC7860 is designed to accommodate applications requiring widely varying power input voltages from 3.5v to 60v. to accommodate the cases where v in drops sig- nificantly, the LTC7860 is guaranteed to operate down to a v in of 3.5v over the full temperature range. the implications of both the uvlo rising and uvlo falling specifications must be carefully considered for low v in operation. the uvlo threshold with v in rising is typi- cally 3.5v ( with a maximum of 3.8 v) and uvlo falling is typically 3.25v ( with a maximum of 3.5 v). the operating input voltage range of the LTC7860 is guaranteed to be 3.5v to 60 v over temperature, but the initial v in ramp must exceed 3.8v to guarantee start-up. for example, figure 5 illustrates LTC7860 operation when an automotive battery droops during a cold crank condition. the typical automotive battery voltage is 12 v to 14.4v, which is more than enough headroom above 3.8 v for the LTC7860 to start up. onboard electronics which are powered by a dc/dc regulator require a minimum supply voltage for seamless operation during the cold crank condition, and the battery may droop close to these minimum supply requirements during a cold crank. the dc/dc regulator should not exacerbate the situation by having excessive voltage drop between the already sup - pressed batter y voltage input and the output of the regulator which powers these electronics. as seen in figure?5, the LTC7860s 100% duty cycle capability allows low dropout from the battery to the output. the drop from v in to v out is determined by the output load current multiplied by the total series resistance of the switching surge stopper. the 3.5 v guaranteed uvlo assures sufficient margin for continuous, uninterrupted operation in extreme cold crank battery drooping conditions. however, additional input capacitance or slower soft start-up time may be required at low v in (e.g. 3.5 v to 4.5 v) in order to limit v in droop caused by inrush currents, especially if the input source has a sufficiently large output impedance. 7860 f06 time v out v battery 12v LTC7860?s 100% duty cycle capability allows v out to ride v in without significant drop-out 5v voltage figure 5. typical automotive cold crank figure 4. internal soft-start (4a) allows soft-start without an external soft-start capacitor and allows soft recovery from (4b) a short-circuit time ~650s (4a) v out v in voltage 7860 f05 internal soft-start induced start-up (no external soft-start capacitor) time short-circuit (4b) v out voltage internal soft-start induced recovery LTC7860 7860f
16 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion m inimum o n -t ime c onsiderations the minimum on-time, t on(min) , is the smallest time duration that the LTC7860 is capable of turning on the power mosfet, and is typically 220 ns. it is determined by internal timing delays and the gate charge required to turn on the mosfet. low duty cycle applications may approach this minimum on-time limit, so care should be taken to ensure that: t on(min) < v out v in(max) ? f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will skip cycles. however, the output voltage will continue to regulate. t hermal c onsidera tions the sustained or static power loss in switch-on opera - tion must be limited so as to ensure suitable maximum component temperatures during all normal operating conditions. the temperature rise of a switching surge stopper is best measured empirically. power loss for the switch-on power paths is i 2 r sw-on and may be calculated according to the equation below. i 2 r sw-on = i 2 tr sense + r ds(on) + r inductor ) the dynamic or transient power loss in protective pwm operation is of concern with respect to component temperature rise and is principally managed by the timer function which sets a maximum time in this mode. thermal mass and thermal resistance play key roles in determining the peak temperatures of components at the point in time when the timer cycles off and shuts down. worst-case operation for a single fault shorted output is typically with the input voltage in the high normal oper - ating range and the output shorted. for this condition, the catch diode is typically the hottest component , as it conducts nearly all the peak current at a high duty cycle. worst-case operation for a single fault input voltage surge is with the input at the maximum expected input voltage or profile at the maximum operational load current. an input voltage surge and output short is a double fault and may not be required. specific fault testing and design margin is determined by system requirements. thermal evaluation and timer setting can be most easily done empirically by observing key component tempera - tures dynamically in various fault conditions. observe peak temperatures with an instrument with sufficient bandwidth to track temperatures, such as an infrared ( ir) camera. one with video capability is ideal. set a maximum temperature rise goal based on compo - nent maximum junction temperature ratings, maximum expected ambient temperature, and allowed junction to case temperature rise. start at lower input voltages and/ or shorter tmr timer settings and increase after empirical system verification and measurement. opti-loop ? c ompensation opti-loop compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors. the ith pin not only allows optimization of the control loop behavior but also provides a test point for the regulator s dc-coupled and ac-filtered closed-loop response. the dc step, rise time and settling at this test point truly reflects the closed- loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at this pin. the ith series r ith -c ith1 filter sets the dominant pole- zero loop compensation. additionally, a small capacitor placed from the ith pin to signal ground, c ith2 , may be required to attenuate high frequency noise. the values can be modified to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback gain and phase. an output LTC7860 7860f
17 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion current pulse of 20% to 100% of full load current having a rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the general goal of opti-loop compensation is to realize a fast but stable ith response with minimal output droop due to the load step. for a detailed explanation of opti-loop compensation, refer to application note 76. faul t timer the LTC7860 is a switching surge stopper. the LTC7860 switches only during startup, during an overcurrent fault and during an input overvoltage surge (protective pwm operation). the primary function of a surge stopper is to limit the output to a programmed maximum voltage during an input voltage surge. limiting the output voltage surge stops the input voltage surge and prevents it from propagating to the system and potentially causing damage. the switching surge stopper external components are op - timized to m inimize total line resistance in normal operation or switch-on mode rather than overload operation. the fault timer limits the switching time during an overload. the fault timer is programmed to allow the switching surge stopper to operate below a safe peak temperature with the pwm power losses in startup, in a current limit fault or in an input voltage surge. since the device shuts down before reaching thermal equilibrium, the power rating can be significantly increased over continuous operation. the fault timer saves system cost and size by allowing component selections to be determined by normal or switch-on mode rather than protective pwm operating mode. the timer indirectly limits the peak switching surge stopper temperatures by limiting the total time spent in higher power loss protective pwm operating mode. fault timer functionality in normal operation the tmr pin voltage is held at ground by the current source tmr pull-down reset i tpdr . when switching is detected, the tmr pull-up current or i tpu pulls up the tmr pin. if the fault is removed and the tmr reverses before reaching the fault set gate off threshold or v gth the tmr pin reverses and pulls to ground by i tpdr . please reference figure?6, timer ( tmr) functional diagram. when the tmr pin exceeds v gth , a fault is detected and the pmos gate is turned off and is held off for a cool down time. once v gth threshold is reached, the pull down current source i tpdc pulls down the tmr until reaching the tmr reset threshold or v rth . the time the pmos gate is shutdown after v gth is reached until the fault is reset is called the cool down time. once the fault is reset, the tmr pin will either pull-down to ground if the fault condition has been cleared or pulled up to v gth if the fault is present. in the case of a persistent fault caused by a short circuit, tmr will continuously retry and shutdown. programming the fault timer the tmr initial set time for fault detection (t seti ) is the total time allowed in pwm regulation before the pmos gate is turned off and shutdown. the constant t seti(1f) is measured and can be used to calculate t seti . the constant includes extension (1 f) to indicate that the time is for a 1 f capacitor and needs to be scaled by c tmr in fs. t seti can be calculated using the equations below: t set1 = c tmr ? v gth i tpu t set1 = c tmr ? t set(1f) cool down gate off 7860 f07 fault timer logic v gth 1.29v v rth 0.24v i tpdc 1.3a i tpdr 40a i tpu 30a normal operation tmr c tmr + ? + ? figure 6. timer (tmr) functional diagram LTC7860 7860f
18 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion the tmr reset cool down time is t rstc and is the total time allowed for the system to cool down before the pmos gate is turned on again after a fault. the constant t rstc(1f) is measured and can be used to calculate t rstc . the constant includes extension (1 f) to indicate that the time is for a 1 f capacitor and needs to be scaled by c tmr in fs. t rstc can be calculated using the equations below: t rstc = c tmr ? v gth C v rth i tpdc t rstc = c tmr ? t rstc(1f) t seti determines how long the switcher is allowed to switch before shutting down. t rstc determines how long the switcher cools down before the pmos gate can be turned on again. for a single fault exceeding t set1 , that shuts down the switching surge stopper, it will restart after the tmr reset cooldown period (t rstc ). in the case of a sustained fault the tmr pin rises after the cool down period expires. in a sustained fault, the tmr pin will pull up from the v rth threshold. the tmr set time repeat after cool down is t setr . the constant t setr(1f) is measured and can be used to calculate t setr . the con- stant includes extension (1 f) to indicate that the value is for a 1 f capacitor and needs to be scaled by c tmr in fs. t setr can be calculated using the equations below: t setr = c tmr ? v gth ? v rth i tpu t setr = c tmr ? t set(1f) in a sustained fault, the switching surge stopper will continuously start, shutdown, cool down and restart at a fixed duty factor. the tmr reset duty cycle in a sustained fault is dty tstr . dty tstr is measured and is calculated according to the equation below. dty tstr = t setr t rstc design example a switching surge stopper can be designed for perfor- mance in normal operation or switch-on mode. its components and thermal design are optimized for normal operation and safely operate through high voltage input surges and/or overcurrent faults. transient operation due to surges and other faults can be survived because the time in regulation is strictly limited when power loss is high. the principle design criterion in normal operation is the total resistance from v in to v out with the resulting power loss and thermal considerations. as a design example, take an application with the fol - lowing specifications: v in = 8 v to 14 v dc with an input voltage transient of 60 v and a decay constant of 500ms, v out ?LTC7860 7860f
19 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion the output voltage is programmed according to: v out = 0.8v ? 1 + r fb2 r fb1 ? ? ? ? ? ? if r fb2 is chosen at 1m, then r fb1 is 48.7k. the freq pin is floated in order to program the switch- ing frequency to 540 khz. the on-time required at 60 v to generate 17.2v output can be calculated as: t on = v out v in ? f = 17.2v 60v ? 540khz = 531ns this on-time is larger than the LTC7860s minimum on- time with sufficient margin to prevent cycle skipping. set the r sense resistor value to ensure the converter can deliver a maximum output current of 5.0 a during an input surge with sufficient margin to account for component variations and worst-case r sense data sheet tolerance. r sense = 85mv 1.05 ? 5a + 3.33a 2 ? ? ? ? ? ? = 12.1m ? the nearest standard value for r sense is 12m. the current limit in normal operation or switch- on mode is not reduced by the ripple current and is: i limit(surge) = 95mv 12m ? = 7.9a r sense power loss for normal operation and at current limit can be calculated according to the equations below. p rsense = i out 2 ? r sense = 5a 2 ? 12m = 300mw p rsense = i out 2 ? r sense = 7.9a 2 ? 12m = 750mw select a 12 m resistor capable of dissipating at least one watt. the average output current limit during a surge is the nor- mal operation current limit minus half the ripple current. the maximum current delivered during a surge will always be less than in normal operation or switch-on mode. i limit(surge) = 95mv 12m ? ? 3.33 2 = 6.25a the total switch-on resistance r sw-on from v in to v out is: r sw-on = r sense + r ds(on) + r inductor r sw-on ?=?12 m?+?11.5m ? (1.6)?+?19 m?=?49.4m the total insertion loss in normal operation or switch- on mode can be calculated below. v drop = i out ? r sw-on = 5a ? 49.4m = 247mw the system will need to be designed to operate in this mode continuously. temperature rise during a surge or fault operation will be limited by the timer. choose an appropriate diode that will handle the power requirements during the surge or fault condition. the diode will never engage during normal operation or switch-on mode but only during a surge or fault. the pds5100-13 schottky diode is selected (v f(5a, 125oc) = 0.60 v) for this application. the continuous current rating of 5 a is sufficient during the tmr limited protective pwm operation. the power dissipated during a surge or fault is. p diode(surge) = 5a ? 1 ? 17.2v 60v ? ? ? ? ? ? ? 0.60v = 2.14w a soft-start time of 8 ms can be programmed through a 0.1f capacitor on the ss pin: c ss = 8ms ? 10a 0.8v = 0.1f LTC7860 7860f
20 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion a 700 ms minimum time limit was chosen based on input surge specifications. we will calculate c tmr for the worst case using t set(1f) minimum and allow for a 10% toler- ance and a 10% variation in capacitance over temperature. we can calculate the required c tmr by using t set(1f)min according to the equation below. c tmr = t setimin t set(1f)min ? 1 0.9 ? 700 37 ? 1 0.9 = 21f the nearest standard value for c tmr is 22 f which results in the tmr set time initial or t seti values given by the equations below. we assume 10% tolerance for capacitors over temperature. t setityp = t set(1f) ? 22f = 44 ? 22f = 968ms t setimin = t set(1f) ? 22 f = 37 ? 22f ? 0.90 = 732ms t setimax = t set(1f) ? 22 f = 50 ? 22f ? 1.1 = 1210ms once t set is tripped there will be a defined tmr reset cool down time t rstctyp . t rstctyp = t rstc(1f ) ? 22f = 732 ? 22f = 16.1s loop compensation components on the ith pin are chosen based on load step transient behavior ( as described under opti-loop compensation) and optimized for stability. compensation is chosen to be 680pf and 10k. g a te d river c omponent p lacement , l ayout and r outing it is important to follow recommended power supply pc board layout practices such as placing external power ele - ments to minimize loop area and inductance in switching paths. be careful to pay particular attention to gate driver component placement, layout and routing. we recommend a ceramic 0.47 f 16 v capacitor with a high quality dielectric such as x5r or x7r. some high current applications with large qg pmos switches may benefit from an even larger c cap capacitance. the effective c cap capacitance should be greater than 0.1 f minimum in all operating conditions. operating voltage and temperature both decrease the rated capacitance to varying degrees depending on dielectric type. the LTC7860 is a pmos controller with an internal gate driver and boot-strapped ldo that regulates the differential cap voltage ( v in C v cap ) to 8 v nominal. the c cap capacitance needs to be large enough to assure stability and provide cycle-to-cycle cur- rent to the pmos switch with minimum series inductance. figure? 7 shows the LTC7860 generic application sche- matic which includes an optional current sense filter and series gate resistor. figure ?8 illustrates the recommended gate driver component placement, layout and routing of the gate, v in , sense and cap pins and key gate driver components. it is recommended that the gate driver layout follow the example shown in figure?8 to assure proper operation and long term reliability. the LTC7860 gate driver should connect to the external power elements in the following manner. first route the v in pin using a single low impedance isolated trace to the positive r sense resistor pad without connection to the v in plane. the reason for this precaution is that the v in pin is internally kelvin connected to the current sense comparator, internal v in power and the pmos gate driver . LTC7860 7860f
21 for more information www.linear.com/LTC7860 connecting the v in pin to the v in power plane adds noise and can result in jitter or instability. figure ?8 shows a single v in trace from the positive r sense pad connected to c sf , c cap , v in pad and c inb . the total trace length to r sense should be minimized and the capacitors c cf , c cap and c inb should be placed near the v in pin of the LTC7860. c cap should be placed near the v in and cap pins. figure ?8 shows c cap placed adjacent to the v in and cap pins with sense routed between the pads. this is the recommended layout and results in the minimum parasitic inductance. the gate driver is capable of providing high peak current. parasitic inductance in the gate drive and the series in - ductance between v in to cap can cause a voltage spike between v in and cap on each switching cycle. the voltage spike can result in electrical over-stress to the gate driver and can result in gate driver failures in extreme cases. it is recommended to follow the example shown in figure ?8 for the placement of c cap as close as is practical. r gate resistor pads can be added with a 1 resistor to allow the damping resistor to be added later. the total length of the gate drive trace to the pmos gate should be minimized and ideally be less than 1 cm. in most cases with a good layout the r gate resistor is not needed. the r gate resistor should be located near the gate pin to re- duce peak current through gate and minimize reflected noise on the gate pin. the r sf and c sf pads can be added with a zero ohm resis- tor for r sf and c sf not populated. in most applications, external filtering is not needed. the current sense filter r sf and c sf can be added later if noise if demonstrated to be a problem. the bypass capacitor c inb is used to locally filter the v in supply. c inb should be tied to the v in pin trace and to the pgnd exposed pad. the c inb positive pad should connect to r sense positive though the v in pin trace. the c inb ground trace should connect to the pgnd exposed pad connection. c sf s rg q1 cap c cap pgnd LTC7860 7860 f08 ss ith freq sgnd run v in tmr sense gate v fbn v fb r ith r sf r sense r gate r freq v in c in + ? c ith c pith c inb c ss route v in power plane to the positive power input to sense resistor. do not connect the v in pin trace. kelvin connect the v in pin, c inb , c sf , c cap connection to r sense + , do not connect this trace to the v in power plane. v in plane z rg figure 7. LTC7860 generic application schematic with optional current sense filter and series gate resistor r gate to q1 gate to r sense + 7860 f09 c inb c cap gate sense cap v in c sf r sf to r sense ? figure 8. LTC7860 recommended gate driver pc board placement, layout and routing the zener z rg and schottky s rg are recommended when driving large power mosfet's and should always be used in combination with r gate equal to 1. we recommend using a 9.1 v zener in parallel with a schottky diode when either the rise or fall time is measured to be greater than 30ns. the purpose of the diodes is to protect the internal multi- amp gate driver against possible electrical over stress when switching the high capacitance power mosfet gate through an inductive gate trace at high current. LTC7860 7860f
22 for more information www.linear.com/LTC7860 a pplica t ions i n f or m a t ion pc b oard l ayout c hecklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC7860. 1. multilayer boards with dedicated ground layers are preferable for reduced noise and for heat sinking pur - poses. use wide rails and/or entire planes for v in , v out and gnd for good filtering and minimal copper loss. if a ground layer is used, then it should be immediately below ( and/or above) the routing layer for the power train components which consist of c in , sense resistor, p- channel mosfet, schottky diode, inductor, and c out . flood unused areas of all layers with copper for better heat sinking. 2. keep signal and power grounds separate except at the point where they are shorted together. short the signal and power ground together only at a single point with a narrow pcb trace ( or single via in a multilayer board). all power train components should be referenced to power ground and all small-signal components (e.g., c ith1 , r freq , c ss etc.) should be referenced to the signal ground. 3. place c in , sense resistor, p-channel mosfet, induc- tor, and primary c out capacitors close together in one compact area. the junction connecting the drain of the p - channel mosfet, cathode of the schottky, and (+) terminal of the inductor ( this junction is com - monly referred to as switch or phase node) should be compact but be large enough to handle the inductor currents without large copper losses. place the sense resistor and source of p-channel mosfet as close as possible to the (+) plate of the c in capacitor(s) that provides the bulk of the ac current ( these are normally the ceramic capacitors), and connect the (C) terminal of the inductor as close as possible to the (C) terminal of the same c in capacitor(s). the high di/dt loop formed by c in , the mosfet, and the schottky diode should have short leads and pcb trace lengths to minimize high frequency emi and voltage stress from inductive ringing. the (+) terminal of the primary c out capacitor(s) which filter the bulk of the inductor ripple current ( these are normally the ceramic capacitors) should also be connected close to the (C) terminal of c in . 4. place pins 7 to 12 facing the power train components. keep high dv/dt signals on gate and switch away from sensitive small-signal traces and components. 5. place the sense resistor close to the (+) terminal of c in and source of p-channel mosfet. use a kelvin (4- wire) connection across the sense resistor and route the traces together as a differential pair into the v in and sense pins. an optional rc filter could be placed near the v in and sense pins to filter the current sense signal. 6. place the feedback divider r fb1/2 as close as possible to the v fb and v fbn pins. the (C) terminal of the feedback divider should connect to the output regulation point and the (+) terminal of the feedback divider should connect to v fb . 7. place the ceramic c cap capacitor as close as possible to the v in and cap pins. this capacitor provides the gate discharging current for the power p-channel mosfet. 8. place small signal components as close to their respec- tive pins as possible. this minimizes the possibility of pcb noise coupling into these pins. give priority to v fb , ith, and freq pins. LTC7860 7860f
23 for more information www.linear.com/LTC7860 typical a pplica t ions 7860 ta02a mp2 si7461dp 3.5v to 60v input, 12v/18v maximum 5a output at 535khz protective pwm: v out clamped 100ms/div v in 10v/div v out 10v/div v tmr 1v/div 7860 ta02b output clamp c tmr = 22f 60v input surge tmr time set initial (t seti ) for tmr timer set initial (t seti ) protective pwm: v out clamped 200ms/div v in 20v/div v out 20v/div v tmr 0.1f 1v/div run 7860 ta02c tmr t seti sgnd output shutdown ss c tmr = 22f v fb 60v input surge ith tmr reset cool down (t rstc ) v fbn for tmr reset cool down (t rstc ) cap protective pwm: v out shutdown freq 2s/div sense v in v in 20v/div gate v out pgnd 20v/div LTC7860 v tmr mp1 si7461dp 1v/div d1 pds5100-13 7860 ta02d l1 6.8h xal6060-682me t rstc c in1 10f r fb2 1m c out1 10f c cap1 0.47f r run1 100k r ith1 10k c ith1 680pf c ith2 10pf v in 60v max 12v nom 3.5v min v out 12v nom 3.5v min 18v max 5a LTC7860 alt v in 60v max 12v nom ?60v min 7860f optional reverse battery protection c ss1 0.1f opt rev c tmr 22f 18v adjustable clamp c ff 3.9pf c tmr = 22f 60v input surge r sense 12m to 18v during a v in surge c sf 100pf r sf opt r fb1 48.7k
24 for more information www.linear.com/LTC7860 typical a pplica t ions + + c tmr 22f q1, q2 bc857bs c sense 100pf c gate 1000pf 7860 ta03a 8v to 100v input, 28v nominal/34v maximum, 10a output at 400khz with non-inverting feedback option v in 25v/div v out 25v/div v tmr 1v/div 7860 ta03c t rstc c in2 opt r3 4.99k r4 4.99k mp2 sum90p10-19l v in 100v max 28v nom 8v min v out 28v nom 8v min 34v max 10a r1 100k r sense 100 d2 stps30m100djf c cap 0.47f r run 100k r freq1 61.9k c ith1 3.3f r ith1 10k c vin1 0.1f c out2 10f 50v 3 d7 cm024l3 4.3v optional reverse battery protection c out1 150f alt v in 100v max 28v nom ?100v min r5 opt rev 100k 34v adjustable clamp d4 cmhz5242b 12v c tmr = 22f mn1 100v input surge tn5325k1g to 34v during a v in surge r2 protective pwm: v out clamped 1k 100ms/div c in3 v in 0.1f 20v/div d5 cmhz5242b 12v v out q5 20v/div pbhv9215z115 v tmr c ss1 1v/div 0.1f 7860 ta03b freq output clamp tmr c tmr = 22f sgnd 100v input surge ss tmr time set initial (t seti ) v fb for tmr timer set initial (t seti ) ith protective pwm: v out clamped v fbn 200ms/div run v in cap 25v/div sense v out v in 25v/div gate v tmr pgnd 1v/div 7860 ta03c t seti output shutdown c tmr = 22f 100v input surge tmr reset cool down (t rstc ) for tmr reset cool down (t rstc ) protective pwm: v out shutdown 2s/div LTC7860 q1 pnp LTC7860 q2 7860f pnp l1 33h 7443633300 r fb4 r sense 7m 10k r g 1 q3 kst43 mp1 sum90p10-19l r fb3 205k c in1 1f 250v 3 r fb1 10k r fb2 10k
25 for more information www.linear.com/LTC7860 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (mse12) 0911 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.22 ?0.38 (.009 ? .015) typ 0.86 (.034) ref 0.650 (.0256) bsc 12 12 11 10 9 8 7 7 detail ?b? 1 6 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane recommended solder pad layout bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 1 2 3 4 5 6 3.00 0.102 (.118 .004) (note 4) 0.406 0.076 (.016 .003) ref 4.90 0.152 (.193 .006) detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc mse package 12-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1666 rev f) LTC7860 7860f
26 for more information www.linear.com/LTC7860 ? linear technology corporation 2015 lt 0215 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC7860 r ela t e d p ar t s typical a pplica t ion part number description comments lt4356-1 high voltage surge stopper 100v overvoltage and overcurrent protection, latch-off and auto-retry option ltc4364 surge stopper with ideal diode 4v to 80v operation; C40v reverse input, C20v reverse output protection lt4363 high voltage surge stopper 100v overvoltage and overcurrent protection, latch-off and auto-retry options ltc4366-1, ltc4366-2 high voltage surge stopper wide operating voltage range: 9v to >500v rugged floating topology ltc3864 low i q , high voltage step-down dc/dc controller with 100% duty cycle fixed frequency 50khz to 850khz, 3.5v v in 60v, 0.8v v out v in , i q = 40a, msop-12e, 3mm 4mm dfn-12 c gate 1000pf c sf 100pf + + 7860 ta04 8v to 100v input, 28v nominal/34v maximum, 10a output at 400khz with inverting feedback option pgnd LTC7860 r fb4 10k r fb3 191k c in2 opt mp2 sum90p10-19l v in 100v max 28v nom 8v min v out 34v max 28v nom 8v min 10a c cap 0.47f r run 100k r freq 61.9k c ith1 3.3nf r ith1 10k c vin1 0.1f optional reverse battery protection alt v in 100v max 28v nom ?100v min c fb1 47pf opt rev l2 33h 7443633300 r g 1 r sense 7m r sf 100 mp1 sum90p10-19l d1 stps30m100djf c in1 1f 250v 3 r fb1 10k c out1 10f 50v 3 c out2 150f r5 100k d3 cmhz5242b 12v mn1 tn5325k1g r2 1k c in3 0.1f d6 cmhz5242b 12v q1 pbhv9215z115 c ss1 0.1f c tmr 22f freq tmr sgnd ss v fb LTC7860 ith 7860f v fbn r fb2 run 10k cap r fbn1 sense v in 10k gate r fbn2 1m mn2 tn5325k1g

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